1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same. More particularly, the present invention relates to a metal via contact of a semiconductor device and a method for fabricating the same.
2. Description of Background Art
As integration density of an integrated circuit device increases, the size of a semiconductor device and interconnection lines thereon becomes smaller and smaller. In order to build more semiconductor devices in a given cell plane with reduced area, three-dimensional semiconductor devices and interconnection lines are being employed. A three-dimensional interconnection line is typically shown in multi-level metallization. Multi-level metallization is carried out as a post-process after a preprocess such as forming a transistor, forming a capacitor and forming a bit line.
An insulator having a low dielectric constant is employed as an interlayer insulating layer formed in the post-process in order to reduce a parasitic capacitance due to metal lines in the same or a different layer. However, in general, the low dielectric layer has a poor gap filling characteristic due to its poor adhesion characteristic to the stepped-underlying layer. In order to avoid the above-mentioned problems, a wetting layer such as a TEOS (Tetra Ethylene Ortho-Silicate) layer is interposed as a base layer between the underlying layer and the low dielectric layer for improving adhesion characteristics. Generally, a HSQ (Hydro SilsesQuioxane) layer by SOG (spin on glass) method is employed as the low dielectric layer. However, hydrogen of the HSQ layer interacts with oxygen from an ashing process for a photoresist pattern used as an etching mask for a contact hole in the interlayer insulating layer. As a result, a crack or the like can occur in the interlayer insulating layer due to water out-diffusion. Therefore, capping the insulating layer as for etching mask or hard mask such as a PE-TEOS (plasma enhanced Tetra Ethylene Ortho-Silicate) layer is additionally formed on the low dielectric layer. After all, a triple layer structure of interlayer insulating layer is used in the low dielectric layer application. Namely, a base layer, a low dielectric layer, and a capping layer structure is employed as the interlayer insulating layer.
In multi-level metallization, aluminium or an aluminium alloy is generally used as a metal line due to its excellent electrical characteristic. For interconnection between metal lines at different level layers, a via hole is formed in the insulator interposed between the metal lines. At this time, the via hole is formed in advance by patterning the insulator to expose a lower metal line. Aluminium is then deposited in the via hole by a sputtering technique and reflowed. However, a recent trend toward high integration density in the semiconductor industry increases the height of the via hole but decreases the aperture of the contact hole, thereby increasing the aspect ratio (ratio of the height to width). As a result, the aluminium cannot fill the deep and narrow contact hole completely, causing a void. Thus, contact resistance is increased or the metal line is cut off.
The low dielectric layer, such as SOG, is relatively fast etched as compared to the base layer and the capping layer. Accordingly, a bowing phenomenon (i.e., the sidewall of the low dielectric layer becomes concave) can occur in a sidewall of the low dielectric layer due to its high etching rate during the etching the triple layer interlayer insulating layer and due to oxygen caused by subsequent plasma ashing.
Bowing of the low dielectric layer results in a reverse slope in the sidewall of the via hole, particularly at the upper half of the bowing part. The reverse slope makes it difficult to fill the via hole completely. FIG. 1 schematically illustrates a semiconductor substrate having a metal via contact as known in the prior art. A PE-TEOS layer 11, a low dielectric layer 13 and a PE-TEOS layer 15 are stacked on a semiconductor substrate 10 sequentially. Due to the bowing phenomenon 21 of the low dielectric layer 13, the metal via contact 17 has a void 19.
Methods for preventing or curing the bowing phenomenon are well-known and are disclosed in some patents, for example, Korean Patent Nos. 1998-000967 and 1997-026317, the disclosures of which are hereby incorporated herein by reference. According to above-cited patents, a radio frequency (RF) etching is carried out in the presence of the photoresist pattern. Accordingly, the photoresist pattern is hard to remove. In addition, when the via hole is formed by only anisotropic etching, overhang can occur in the process of sputtering due to a smaller aperture size of the hole. If the RF etching is carried out after the photoresist pattern is formed, the top portion of the via hole may be over-etched thereby enlarging the aperture size of the via hole to an unacceptable value. This enlargement of the aperture size to an unacceptable value can cause an electrical bridge between adjacent metal lines.
It is a feature of an embodiment of the present invention to provide a metal via contact without a void and a method for fabricating the metal via contact.
It is another feature of an embodiment of the present invention to provide a metal via contact without an electrical bridge between adjacent metal lines and a method for fabricating the metal via contact.
In order to solve the aforementioned problems and provide the above and other features of the present invention, a metal via contact of a semiconductor device is provided. The semiconductor device includes a multi-layer structure of an interlayer insulating layer comprising an interlayer insulating layer including a first insulating, a low dielectric SOG (Spin On Glass) layer, a second insulating layer and a silicon oxynitride layer formed in that order on a semiconductor substrate, and a metal via contact formed in the interlayer insulating layer, and tapered from a top surface of the interlayer insulating layer to a bottom surface of the interlayer insulating layer and formed by a sputtering technique.
The first and second insulating layers are formed of a CVD silicon oxide layer. Preferably, the first and second insulating layers are formed of PE-TEOS oxide layer. Preferably, the low dielectric SOG layer is formed of Hydro SilsesQuioxane (HSQ).
In order to solve the aforementioned problems and provide the above and other features of the present invention, a method for fabricating a metal via contact of a semiconductor device is provided. The method includes sequentially forming a first insulating layer, a low dielectric SOG (Spin On Glass) layer, a second insulating layer and a silicon oxynitride (SiON) layer on a semiconductor substrate forming a photoresist pattern; using the photoresist pattern as an etching mask and wet etching the silicon oxynitride layer and a portion of the second insulating layer; using the same photoresist pattern as an etching mask and anisotropically etching a remaining portion of the second insulating layer, the low dielectric SOG layer and the first insulating layer to form a via hole exposing a predetermined portion of the semiconductor substrate; removing the photoresist pattern; using radio frequency (RF) etching to remove a reverse slope of the via hole; and forming a metal plug in the via hole.
In an alternate embodiment of the present invention, the removal of the photoresist pattern is carried out by ashing or a combination of ashing and stripping. The radio frequency (RF) etching continues until the silicon oxynitride layer is completely removed. The formation of the metal plug comprises sputtering and heat reflow techniques. The sputtering technique uses aluminium as a sputtering source. At this time, the radio frequency (RF) etching is carried out in a sputtering apparatus for the metal plug, thereby providing an in-situ process for the radio frequency etching and forming the metal plug. The radio frequency (RF) etching is carried out so as not to enlarge a top width of the via hole beyond an undercut portion.
These and other features and advantages of the invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.